A first conventional transversal bipolar transistor is described in the Japanese Patent Kokai No. 62-141760. In the first conventional transversal bipolar transistor, p-epitaxial regions are formed on an insulating substrate, and polysilicon layers are formed on silicon dioxide films formed to cross the central portions of the p-epitaxial regions. Impurities of n-conductivity type are injected into the p-epitaxial regions by using the polysilicon layers and silicon dioxide films as masks, so that a n-emitter region and a n-collector region are formed on the both sides of one of the p-epitaxial regions to provide the transversal bipolar transistor, and a n-source region and a n-drain region are formed on the both sides of the remaining one of the p-epitaxial region to provide the MOS transistor.
A second conventional transversal bipolar transistor is described in the Japanese Patent Kokai No. 1-211969. In the second conventional transversal bipolar transistor, a n-impurity region is selectively formed on a semi-insulating semiconductor substrate, and a p-impurity region is formed in the central portion of the n-impurity region to provide a base region, so that the remaining portions of the n-impurity region are for emitter and collector regions.
In the first conventional transversal bipolar transistor, however, there are disadvantages in that a width of the base region is difficult to be narrow, and high speed operation is hindered, because the width of the base region becomes large effectively in operation in which carriers emitted from the emitter region at the range of high current density propagate through the insulating substrate having a lower barrier, when a concentration of the base region is higher than that of the insulating substrate.
In the second conventional transversal bipolar transistor, there is a disadvantage in that it is difficult to be fabricated simultaneously with the fabrication of a high performance vertical bipolar transistor. For instance, it is impossible to fabricate a semiconductor integrated circuit having a vertical NPN bipolar transistor and a transversal PNP bipolar transistor which operates with high speed and low power consumption under a small number of steps and a low cost.